\doxysection{stm32h7xx\+\_\+hal\+\_\+rcc\+\_\+ex.\+h}
\hypertarget{stm32h7xx__hal__rcc__ex_8h_source}{}\label{stm32h7xx__hal__rcc__ex_8h_source}\index{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_rcc\_ex.h@{C:/Users/ASUS/Desktop/dm-\/ctrlH7-\/balance-\/9025test/Drivers/STM32H7xx\_HAL\_Driver/Inc/stm32h7xx\_hal\_rcc\_ex.h}}
\mbox{\hyperlink{stm32h7xx__hal__rcc__ex_8h}{Go to the documentation of this file.}}
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\DoxyCodeLine{03786\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CRS\_CLEAR\_IT(\_\_INTERRUPT\_\_)\ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03787\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ if(((\_\_INTERRUPT\_\_)\ \&\ RCC\_CRS\_IT\_ERROR\_MASK)\ !=\ 0U)\ \(\backslash\)}}
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\DoxyCodeLine{03789\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ WRITE\_REG(CRS-\/>ICR,\ CRS\_ICR\_ERRC\ |\ ((\_\_INTERRUPT\_\_)\ \&\ \string~RCC\_CRS\_IT\_ERROR\_MASK));\ \(\backslash\)}}
\DoxyCodeLine{03790\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \(\backslash\)}}
\DoxyCodeLine{03791\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ else\ \(\backslash\)}}
\DoxyCodeLine{03792\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \(\backslash\)}}
\DoxyCodeLine{03793\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ WRITE\_REG(CRS-\/>ICR,\ (\_\_INTERRUPT\_\_));\ \(\backslash\)}}
\DoxyCodeLine{03794\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \(\backslash\)}}
\DoxyCodeLine{03795\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03796\ }
\DoxyCodeLine{03810\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CRS\_GET\_FLAG(\_\_FLAG\_\_)\ \ (READ\_BIT(CRS-\/>ISR,\ (\_\_FLAG\_\_))\ ==\ (\_\_FLAG\_\_))}}
\DoxyCodeLine{03811\ }
\DoxyCodeLine{03826\ }
\DoxyCodeLine{03827\ \textcolor{comment}{/*\ CRS\ Flag\ Error\ Mask\ */}}
\DoxyCodeLine{03828\ \textcolor{preprocessor}{\#define\ RCC\_CRS\_FLAG\_ERROR\_MASK\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((uint32\_t)(RCC\_CRS\_FLAG\_TRIMOVF\ |\ RCC\_CRS\_FLAG\_SYNCERR\ |\ RCC\_CRS\_FLAG\_SYNCMISS))}}
\DoxyCodeLine{03829\ }
\DoxyCodeLine{03830\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CRS\_CLEAR\_FLAG(\_\_FLAG\_\_)\ \ \ \ \ do\ \{\ \(\backslash\)}}
\DoxyCodeLine{03831\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ if(((\_\_FLAG\_\_)\ \&\ RCC\_CRS\_FLAG\_ERROR\_MASK)\ !=\ 0U)\ \(\backslash\)}}
\DoxyCodeLine{03832\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \(\backslash\)}}
\DoxyCodeLine{03833\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ WRITE\_REG(CRS-\/>ICR,\ CRS\_ICR\_ERRC\ |\ ((\_\_FLAG\_\_)\ \&\ \string~RCC\_CRS\_FLAG\_ERROR\_MASK));\ \(\backslash\)}}
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\DoxyCodeLine{03835\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ else\ \(\backslash\)}}
\DoxyCodeLine{03836\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \{\ \(\backslash\)}}
\DoxyCodeLine{03837\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ WRITE\_REG(CRS-\/>ICR,\ (\_\_FLAG\_\_));\ \(\backslash\)}}
\DoxyCodeLine{03838\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ \(\backslash\)}}
\DoxyCodeLine{03839\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \}\ while(0)}}
\DoxyCodeLine{03840\ }
\DoxyCodeLine{03849\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CRS\_FREQ\_ERROR\_COUNTER\_ENABLE()\ \ SET\_BIT(CRS-\/>CR,\ CRS\_CR\_CEN)}}
\DoxyCodeLine{03850\ }
\DoxyCodeLine{03855\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CRS\_FREQ\_ERROR\_COUNTER\_DISABLE()\ CLEAR\_BIT(CRS-\/>CR,\ CRS\_CR\_CEN)}}
\DoxyCodeLine{03856\ }
\DoxyCodeLine{03862\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CRS\_AUTOMATIC\_CALIB\_ENABLE()\ \ \ \ \ SET\_BIT(CRS-\/>CR,\ CRS\_CR\_AUTOTRIMEN)}}
\DoxyCodeLine{03863\ }
\DoxyCodeLine{03868\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CRS\_AUTOMATIC\_CALIB\_DISABLE()\ \ \ \ CLEAR\_BIT(CRS-\/>CR,\ CRS\_CR\_AUTOTRIMEN)}}
\DoxyCodeLine{03869\ }
\DoxyCodeLine{03880\ \textcolor{preprocessor}{\#define\ \_\_HAL\_RCC\_CRS\_RELOADVALUE\_CALCULATE(\_\_FTARGET\_\_,\ \_\_FSYNC\_\_)\ \ (((\_\_FTARGET\_\_)\ /\ (\_\_FSYNC\_\_))\ -\/\ 1U)}}
\DoxyCodeLine{03881\ }
\DoxyCodeLine{03882\ }
\DoxyCodeLine{03886\ }
\DoxyCodeLine{03887\ }
\DoxyCodeLine{03891\ }
\DoxyCodeLine{03892\ }
\DoxyCodeLine{03893\ \textcolor{comment}{/*\ Exported\ functions\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{03897\ }
\DoxyCodeLine{03901\ \mbox{\hyperlink{stm32h7xx__hal__def_8h_a63c0679d1cb8b8c684fbb0632743478f}{HAL\_StatusTypeDef}}\ HAL\_RCCEx\_PeriphCLKConfig(\mbox{\hyperlink{struct_r_c_c___periph_c_l_k_init_type_def}{RCC\_PeriphCLKInitTypeDef}}\ \ *PeriphClkInit);}
\DoxyCodeLine{03902\ \textcolor{keywordtype}{void}\ HAL\_RCCEx\_GetPeriphCLKConfig(\mbox{\hyperlink{struct_r_c_c___periph_c_l_k_init_type_def}{RCC\_PeriphCLKInitTypeDef}}\ \ *PeriphClkInit);}
\DoxyCodeLine{03903\ uint32\_t\ HAL\_RCCEx\_GetPeriphCLKFreq(uint64\_t\ PeriphClk);}
\DoxyCodeLine{03904\ uint32\_t\ HAL\_RCCEx\_GetD1PCLK1Freq(\textcolor{keywordtype}{void});}
\DoxyCodeLine{03905\ uint32\_t\ HAL\_RCCEx\_GetD3PCLK1Freq(\textcolor{keywordtype}{void});}
\DoxyCodeLine{03906\ uint32\_t\ HAL\_RCCEx\_GetD1SysClockFreq(\textcolor{keywordtype}{void});}
\DoxyCodeLine{03907\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCCEx\_GetPLL1ClockFreq(\mbox{\hyperlink{struct_p_l_l1___clocks_type_def}{PLL1\_ClocksTypeDef}}\ *PLL1\_Clocks);}
\DoxyCodeLine{03908\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCCEx\_GetPLL2ClockFreq(\mbox{\hyperlink{struct_p_l_l2___clocks_type_def}{PLL2\_ClocksTypeDef}}\ *PLL2\_Clocks);}
\DoxyCodeLine{03909\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCCEx\_GetPLL3ClockFreq(\mbox{\hyperlink{struct_p_l_l3___clocks_type_def}{PLL3\_ClocksTypeDef}}\ *PLL3\_Clocks);}
\DoxyCodeLine{03913\ }
\DoxyCodeLine{03917\ \textcolor{keywordtype}{void}\ HAL\_RCCEx\_WakeUpStopCLKConfig(uint32\_t\ WakeUpClk);}
\DoxyCodeLine{03918\ \textcolor{keywordtype}{void}\ HAL\_RCCEx\_KerWakeUpStopCLKConfig(uint32\_t\ WakeUpClk);}
\DoxyCodeLine{03919\ \textcolor{keywordtype}{void}\ HAL\_RCCEx\_EnableLSECSS(\textcolor{keywordtype}{void});}
\DoxyCodeLine{03920\ \textcolor{keywordtype}{void}\ HAL\_RCCEx\_DisableLSECSS(\textcolor{keywordtype}{void});}
\DoxyCodeLine{03921\ \textcolor{keywordtype}{void}\ HAL\_RCCEx\_EnableLSECSS\_IT(\textcolor{keywordtype}{void});}
\DoxyCodeLine{03922\ \textcolor{keywordtype}{void}\ HAL\_RCCEx\_LSECSS\_IRQHandler(\textcolor{keywordtype}{void});}
\DoxyCodeLine{03923\ \textcolor{keywordtype}{void}\ HAL\_RCCEx\_LSECSS\_Callback(\textcolor{keywordtype}{void});}
\DoxyCodeLine{03924\ \textcolor{preprocessor}{\#if\ defined(DUAL\_CORE)}}
\DoxyCodeLine{03925\ \textcolor{keywordtype}{void}\ HAL\_RCCEx\_EnableBootCore(uint32\_t\ RCC\_BootCx);}
\DoxyCodeLine{03926\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*DUAL\_CORE*/}\textcolor{preprocessor}{}}
\DoxyCodeLine{03927\ \textcolor{preprocessor}{\#if\ defined(RCC\_GCR\_WW1RSC)}}
\DoxyCodeLine{03928\ \textcolor{keywordtype}{void}\ HAL\_RCCEx\_WWDGxSysResetConfig(uint32\_t\ RCC\_WWDGx);}
\DoxyCodeLine{03929\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*RCC\_GCR\_WW1RSC*/}\textcolor{preprocessor}{}\textcolor{preprocessor}{}}
\DoxyCodeLine{03933\ }
\DoxyCodeLine{03934\ }
\DoxyCodeLine{03938\ }
\DoxyCodeLine{03939\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCCEx\_CRSConfig(\textcolor{keyword}{const}\ \mbox{\hyperlink{struct_r_c_c___c_r_s_init_type_def}{RCC\_CRSInitTypeDef}}\ *pInit);}
\DoxyCodeLine{03940\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCCEx\_CRSSoftwareSynchronizationGenerate(\textcolor{keywordtype}{void});}
\DoxyCodeLine{03941\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCCEx\_CRSGetSynchronizationInfo(\mbox{\hyperlink{struct_r_c_c___c_r_s_synchro_info_type_def}{RCC\_CRSSynchroInfoTypeDef}}\ *pSynchroInfo);}
\DoxyCodeLine{03942\ uint32\_t\ HAL\_RCCEx\_CRSWaitSynchronization(uint32\_t\ Timeout);}
\DoxyCodeLine{03943\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCCEx\_CRS\_IRQHandler(\textcolor{keywordtype}{void});}
\DoxyCodeLine{03944\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCCEx\_CRS\_SyncOkCallback(\textcolor{keywordtype}{void});}
\DoxyCodeLine{03945\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCCEx\_CRS\_SyncWarnCallback(\textcolor{keywordtype}{void});}
\DoxyCodeLine{03946\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCCEx\_CRS\_ExpectedSyncCallback(\textcolor{keywordtype}{void});}
\DoxyCodeLine{03947\ \textcolor{keywordtype}{void}\ \ \ \ \ HAL\_RCCEx\_CRS\_ErrorCallback(uint32\_t\ Error);}
\DoxyCodeLine{03948\ }
\DoxyCodeLine{03952\ }
\DoxyCodeLine{03956\ }
\DoxyCodeLine{03957\ \textcolor{comment}{/*\ Private\ macros\ -\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/-\/*/}}
\DoxyCodeLine{03964\ }
\DoxyCodeLine{03965\ \textcolor{preprocessor}{\#define\ IS\_RCC\_PLL2CLOCKOUT\_VALUE(VALUE)\ (((VALUE)\ ==\ RCC\_PLL2\_DIVP)\ ||\ \(\backslash\)}}
\DoxyCodeLine{03966\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((VALUE)\ ==\ RCC\_PLL2\_DIVQ)\ \ ||\ \(\backslash\)}}
\DoxyCodeLine{03967\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((VALUE)\ ==\ RCC\_PLL2\_DIVR))}}
\DoxyCodeLine{03968\ }
\DoxyCodeLine{03969\ \textcolor{preprocessor}{\#define\ IS\_RCC\_PLL3CLOCKOUT\_VALUE(VALUE)\ (((VALUE)\ ==\ RCC\_PLL3\_DIVP)\ ||\ \(\backslash\)}}
\DoxyCodeLine{03970\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((VALUE)\ ==\ RCC\_PLL3\_DIVQ)\ ||\ \(\backslash\)}}
\DoxyCodeLine{03971\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((VALUE)\ ==\ RCC\_PLL3\_DIVR))}}
\DoxyCodeLine{03972\ }
\DoxyCodeLine{03973\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP2R\_USART16SEL)}}
\DoxyCodeLine{03974\ \textcolor{preprocessor}{\#define\ IS\_RCC\_USART16CLKSOURCE(SOURCE)\ (((SOURCE)\ ==\ RCC\_USART16CLKSOURCE\_D2PCLK2)||\ \(\backslash\)}}
\DoxyCodeLine{03975\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART16CLKSOURCE\_PLL2)\ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{03976\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART16CLKSOURCE\_PLL3)\ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{03977\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART16CLKSOURCE\_CSI)\ \ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{03978\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART16CLKSOURCE\_LSE)\ \ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{03979\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART16CLKSOURCE\_HSI))}}
\DoxyCodeLine{03980\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{03981\ \textcolor{preprocessor}{\#define\ IS\_RCC\_USART16CLKSOURCE(SOURCE)\ (((SOURCE)\ ==\ RCC\_USART16CLKSOURCE\_D2PCLK2)||\ \(\backslash\)}}
\DoxyCodeLine{03982\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART16CLKSOURCE\_CDPCLK2)||\ \(\backslash\)}}
\DoxyCodeLine{03983\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART16CLKSOURCE\_PLL2)\ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{03984\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART16CLKSOURCE\_PLL3)\ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{03985\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART16CLKSOURCE\_CSI)\ \ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{03986\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART16CLKSOURCE\_LSE)\ \ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{03987\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART16CLKSOURCE\_HSI))}}
\DoxyCodeLine{03988\ \textcolor{comment}{/*\ alias*/}}
\DoxyCodeLine{03989\ \textcolor{preprocessor}{\#define\ IS\_RCC\_USART16910CLKSOURCE\ \ \ \ IS\_RCC\_USART16CLKSOURCE}}
\DoxyCodeLine{03990\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP2R\_USART16SEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{03991\ }
\DoxyCodeLine{03992\ \textcolor{preprocessor}{\#if\ defined(RCC\_D2CCIP2R\_USART28SEL)}}
\DoxyCodeLine{03993\ \textcolor{preprocessor}{\#define\ IS\_RCC\_USART234578CLKSOURCE(SOURCE)\ (((SOURCE)\ ==\ RCC\_USART234578CLKSOURCE\_D2PCLK1)||\ \(\backslash\)}}
\DoxyCodeLine{03994\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART234578CLKSOURCE\_PLL2)\ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{03995\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART234578CLKSOURCE\_PLL3)\ \ \ ||\ \(\backslash\)}}
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\DoxyCodeLine{03999\ \textcolor{preprocessor}{\#else}}
\DoxyCodeLine{04000\ \textcolor{preprocessor}{\#define\ IS\_RCC\_USART234578CLKSOURCE(SOURCE)\ (((SOURCE)\ ==\ RCC\_USART234578CLKSOURCE\_D2PCLK1)||\ \(\backslash\)}}
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\DoxyCodeLine{04002\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART234578CLKSOURCE\_PLL2)\ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{04003\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART234578CLKSOURCE\_PLL3)\ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{04004\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART234578CLKSOURCE\_CSI)\ \ \ \ ||\ \(\backslash\)}}
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\DoxyCodeLine{04006\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART234578CLKSOURCE\_HSI))}}
\DoxyCodeLine{04007\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ RCC\_D2CCIP2R\_USART28SEL\ */}\textcolor{preprocessor}{}}
\DoxyCodeLine{04008\ }
\DoxyCodeLine{04009\ \textcolor{preprocessor}{\#define\ IS\_RCC\_USART1CLKSOURCE(SOURCE)\ (((SOURCE)\ ==\ RCC\_USART1CLKSOURCE\_D2PCLK2)||\ \(\backslash\)}}
\DoxyCodeLine{04010\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART1CLKSOURCE\_PLL2)\ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{04011\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART1CLKSOURCE\_PLL3)\ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{04012\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART1CLKSOURCE\_CSI)\ \ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{04013\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART1CLKSOURCE\_LSE)\ \ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{04014\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART1CLKSOURCE\_HSI))}}
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\DoxyCodeLine{04016\ \textcolor{preprocessor}{\#define\ IS\_RCC\_USART2CLKSOURCE(SOURCE)\ (((SOURCE)\ ==\ RCC\_USART2CLKSOURCE\_D2PCLK1)||\ \(\backslash\)}}
\DoxyCodeLine{04017\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART2CLKSOURCE\_PLL2)\ \ \ ||\ \(\backslash\)}}
\DoxyCodeLine{04018\ \textcolor{preprocessor}{\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ((SOURCE)\ ==\ RCC\_USART2CLKSOURCE\_PLL3)\ \ \ ||\ \(\backslash\)}}
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\DoxyCodeLine{04455\ \textcolor{preprocessor}{\#define\ IS\_RCC\_CRS\_ERRORLIMIT(\_\_VALUE\_\_)\ \ \ (((\_\_VALUE\_\_)\ <=\ 0xFFU))}}
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\DoxyCodeLine{04457\ \textcolor{preprocessor}{\#define\ IS\_RCC\_CRS\_HSI48CALIBRATION(\_\_VALUE\_\_)\ (((\_\_VALUE\_\_)\ <=\ 0x3FU))}}
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\DoxyCodeLine{04459\ \textcolor{preprocessor}{\#define\ IS\_RCC\_CRS\_FREQERRORDIR(\_\_DIR\_\_)\ \ \ (((\_\_DIR\_\_)\ ==\ RCC\_CRS\_FREQERRORDIR\_UP)\ ||\ \(\backslash\)}}
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\DoxyCodeLine{04479\ \textcolor{preprocessor}{\#endif}}
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\DoxyCodeLine{04481\ \textcolor{preprocessor}{\#endif\ }\textcolor{comment}{/*\ STM32H7xx\_HAL\_RCC\_EX\_H\ */}\textcolor{preprocessor}{}}
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